Analog to digital converter

ABSTRACT

The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets.

[0001] This invention relates to integrated circuits in which repetitivecells-are matched for optimal circuit operation. More particularly, thisinvention relates to integrated circuits in which the effects of anycell mismatches are minimized. The invention is particularly adapted tobe used in analog-to-digital converters. The invention additionallyrelates to methods of minimizing the effects of cell mismatches on celloutputs.

BACKGROUND OF THE INVENTION

[0002] Various types of systems have been provided in the prior art forconverting an analog voltage to digital signals (currents or voltages)representative of such analog voltage. One type of system often used inthe prior art to provide such conversion has been known as a “flashconverter”. In a flash converter, an analog input signal representativeof the analog value to be converted digitally is introduced to a firstinput of a differential amplifier in each of a plurality of repetitivecells. An individual one of a plurality of progressive fractions in areference voltage is introduced to a second input of such differentialamplifier.

[0003] In the prior art, the differential amplifier in each cell mayhave first and-second branches each including a transistor such as aCMOS transistor, each transistor having a gate, a source and a drain.The gates of the transistors in the first and second branchesrespectively receive the first and second inputs. The sources of the two(2) transistors in each differential amplifier have a common connectionto a source of a substantially constant current. Load bearing currentsflow through the transistors in the branches in each differentialamplifier in accordance with the relative values of the voltages on thegates of the transistors, the sum of these currents being thesubstantially constant current.

[0004] Thus, a first output such as a binary “1” is produced in acomparator when the input voltage exceeds the particular fraction of thereference voltage introduced to the differential amplifier. Similarly, asecond output such as a binary “0” is produced in the comparator whenthe input voltage is less than the particular fraction of the referencevoltage introduced to the differential amplifier.

[0005] Exclusive “or” networks compare the outputs from successive pairsof comparators. An output indication is provided by the exclusive “or”network in which one of the comparator inputs is a-binary “1” and theother input is a binary “0”. Each exclusive “or” network is programmedto provide digital indications of the input voltage represented by such“or” network.

[0006] The analog-to-digital converter discussed above is advantageousin that it can operate at high frequencies such as in the megahertzrange. However, in order to determine the value of the input voltagewith some accuracy and to convert this input voltage to thecorresponding digital signals, a large number of amplifiers have to beprovided. For example, for a converter providing a conversion of ananalog signal to ten (10) binary bits, ten hundred and twenty four(1024) differential amplifiers and ten hundred and twenty three (1023)comparators would be required. When the input voltage is approximatelytwo volts, each differential amplifier would have to provide adistinction between adjacent amplifiers in the order of two millivolts(2 mV.) Since this voltage is relatively small, it presents difficultiesin the operation of the comparators.

[0007] The flash types of analog-to-digital converters have generallybeen disposed-on an integrated circuit (IC) chip, particularly for anumber of bits greater than about seven (7). Imperfections in thesilicon substrate of the chip and in the methods of manufacturing thechip have produced mismatches between the outputs from successive pairsof differential amplifiers. These mismatches have caused errors to beproduced in the stages providing the comparison between the input andreference voltages introduced to the differential amplifier. Thesemismatches have caused errors to be produced in the digital indicationsproduced to represent the analog input signal.

[0008] Various attempts have been made to compensate for the cellmismatches produced in the converter of the prior art. For example, U.S.Pat. No. 5,175,550 issued to Kevin M. Kattman and Jeffrey G. Barrow for“Repetitive Cell Matching Technique for Integrated Circuits” andassigned of record to Analog Devices, Inc. discloses a system for, andmethod of providing, such compensation. In the '550 patent, a pluralityof cells are provided each including a differential amplifier defined bytwo (2) branches. A transistor is provided in each branch. Thetransistor in a first one of the branches in each cell receives an inputsignal and the transistor in a second one of the branches in each cellreceives an individual one of the progressive fractions of a referencevoltage.

[0009] In the '550 patent, a plurality of load resistors are providedeach connected to an individual one of the transistors in one of thefirst and second branches in an individual one of the cells to receivethe load current flowing through such transistor. In addition, a firstplurality of averaging resistors is provided each connected between thecorresponding output terminals of the transistors in the first branchesof successive pairs of the repetitive cells. A second plurality ofaveraging resistors is also provided each connected between thecorresponding output terminals of the transistors in the second branchesof successive pairs of the repetitive cells.

[0010] The system disclosed in the '550 patent operates to average thecell mismatches over a plurality of cells so as to reduce theinaccuracies resulting in the converted digital signals from the cellmismatches. Because of this, the system disclosed in the '550 patentreduces the differential non-linearities and integral non-linearities inthe analog-to-digital converter formed from the plurality of cells. Thelower the values of the averaging resistors that are provided in thefirst and second pluralities in the '550 patent, generally the greateris the improvement in the accuracy of the conversion from the analogvalue to the digital value. However, the gain in the system is reducedin the prior art when the values of the averaging resistors are reduced.Furthermore, the lower the gain, the more the offset in the comparatorswill become dominant. This limits the amount that the gain can bereduced in the prior art. Because of this, in the optimum, thedifferential non-linearity of the system disclosed in the '550 patent isreduced by a factor of approximately three (3) (1.58 bits) in comparisonto the A-D converters of the prior art.

[0011] Although the system disclosed in the '550 patent provides asignificant improvement in the accuracy of the digital output signalsover the prior art, this improvement is small compared to theimprovement produced in the accuracy of the output digital signals bythe system disclosed and claimed in application Ser. No. 08/792,941filed by Klaas Bult on Jan. 21, 1977, for an “Analog-to-DigitalConverter” and assigned of record to the assignee of record of thisapplication. For example, the system disclosed and claimed inapplication Ser. No. 08/792,941 provides an improvement of thedifferential non-linearity in the accuracy of the output-digital signalsby as much as 17.3 (4 bits) when averaging over sixteen (16) stages wasperformed. The system disclosed and claimed in application Ser. No.08/792,941 additionally averages currents from approximately sixteen(16) stages and produces an approximately two (2) binary bit gain inintegral non-linearity.

[0012] In one embodiment of the invention disclosed and claimed inapplication Ser. No. 08/792,941, an analog-to-digital converter (ADC)formed on an integrated circuit chip from a plurality of cells includesa differential amplifier having first and second branches. The branchesin each cell respectively have first and second transistors, oneresponsive to an input voltage and the other responsive to an individualone of progressive fractions of a reference voltage. The relativeoutputs from the branches for each cell are dependent upon the relativevalues of the two voltages introduced to the cell.

[0013] To minimize cell mismatches and the-effects of these mismatcheson cell outputs, first and second sets of averaging impedances,preferably resistors, are respectively connected in the system ofapplication Ser. No. 08/792,941 between the output terminals of thefirst branch transistors, and between the output terminals of the secondbranch transistors, in successive pairs of cells.

[0014] Current sources connected to the output terminals of thetransistors in the first and second branches in the system ofapplication Ser. No. 08/792,941 have characteristics (preferablyimpedances approaching infinity) to force the signal bearing currentsfrom the transistors to flow through the impedances in the first andsecond sets. The impedances have relatively low values, particularly incomparison to the impedances in the current sources, to reduce cellmismatches.

[0015] First and second resistive strips on the chip may be tapped atprogressive positions in the system disclosed and claimed in applicationSer. No. 08/792,941 to respectively define the impedances in the firstand second sets. One end of each strip may be connected to the oppositeend of the other strip to define a closed impedance loop and to minimizeerrors resulting from the averaging resistors-at the ends of the strip.

[0016] The system disclosed and claimed in Ser. No. 08/792,941application has certain important advantages over the prior artincluding the system of the '550 patent. These advantages provideconsiderable improvements in differential non-linearity and integralnon-linearity specified above. These considerable improvements result inpart from the fact that the system of this invention uses currentsources (of a very high impedance value) and further uses the averagingresistances with impedance values as the load elements whereas the '550patent uses resistors (not the averaging impedances) as the loaddevices.

[0017] The considerable improvements in the embodiment of the systemdisclosed and claimed in application Ser. No. 08/792,941 also resultfrom the fact that the averaging impedances in the system of thisinvention constitute the actual signal current carrying load elements.In contrast, in the system of this invention, applicant provides acircular (or looped) termination of the averaging impedances.Furthermore, in the '550 patent, the last resistors in the first andsecond pluralities are terminated on an open ended basis.

[0018] Although the system in application Ser. No. 08/792,941 isdisclosed primarily for use in an analog-to-digital converter, it hasutility in other systems as well. For example, the system disclosed inapplication Ser. No. 08/792,941 may be used in a digital-to-analogconverter. Actually, the system may be used in any embodiment where aplurality of repetitive cells are provided, particularly when therepetitive cells are disposed on an integrated circuit chip.

BRIEF DESCRIPTION OF THE INVENTION

[0019] In one embodiment of the invention, the output of each cell in anA-D converter in an IC chip is dependent upon the relative values of aninput voltage and an individual one of progressive fractions of areference voltage respectively introduced to the branches in adifferential amplifier. To minimize output errors from cell mismatches,first and second sets of averaging impedances, preferably resistors, arerespectively connected between the output terminals in the firstbranches, and the output terminals in the second branches, in successivepairs of cells. The impedances have relatively low values, particularlycompared to the impedances of current sources connected to the branchoutput terminals.

[0020] First and second resistive strips on the chip may be tapped atprogressive positions to respectively define the impedances in the firstand second sets. One end of each strip may be connected to the oppositeend of the other strip to define a closed impedance loop for minimizingaveraging errors at the strip ends. Different fractions of the referencevoltage are associated with each individual impedance in the first andsecond sets. Such reference voltage fractions associated with eachindividual impedance have a particular repetitive relationship.

[0021] In this way, the number of output terminals and cell mismatchesare reduced. The different outputs at each individual impedance aredetermined for the progressive fractions of the reference voltage atsuch impedance. Successive voltage fractions for each impedance haveopposite polarities to provide a folding relationship. Such outputs maybe cascaded to further reduce cell mismatches and the number of outputterminals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In the drawings:

[0023]FIG. 1 is a simplified circuit diagram of a conventional flashconverter of the prior art;

[0024]FIG. 2 is a generalized circuit diagram of an integrated circuitemploying, in the prior art as shown in the '550 patent, a plurality ofrespective cells and averaging impedances for reducing the effects ofcell mismatches;

[0025]FIG. 3 is a diagram indicating the reducing effect produced on acell mismatch in a single cell by the electrical circuitry of the priorart as shown in FIG. 2;

[0026]FIG. 4 is a simplified circuit diagram of a flash converter of thetype shown in the '550 patent;

[0027]FIG. 5 is a simplified diagram of a flash converter disclosed andclaimed in application Ser. No. 08/792,941;

[0028]FIG. 6 is a simplified circuit diagram of an amplifier which maybe included in the system shown in FIG. 5 to provide high impedancevalues approaching infinity;

[0029]FIG. 7a shows curves of integral non-linearity with and withoutthe features of the system disclosed and claimed in application Ser. No.08/792,941 and illustrates the considerable decrease in integralnon-linearity produced by applicant's invention;

[0030]FIG. 7b shows curves of differential non-linearity with andwithout the features of the system disclosed and claimed in applicationSer. No. ______ and illustrates the considerable decrease indifferential non-linearity produced by such system;

[0031]FIG. 8 is a diagram schematically illustrating the input ranges ofindividual cells in the circuitry shown in FIG. 5 as a result of theinclusion of the features of the system disclosed and claimed inapplication Ser. No. 08/792,941;

[0032]FIG. 9 illustrates an embodiment included in the system disclosedand claimed in application Ser. No. 08/792,941 for replacing theimpedances in the system of FIG. 5 by strips of resistive materialdeposited on an integrated circuit chip;

[0033]FIG. 10 illustrates an additional embodiment of the systemdisclosed and claimed in application Ser. No. 08/792,941 wherein crossconnections are provided between the resistive strips defining theaveraging resistors shown in FIG. 9 to minimize the effects of open-endterminations of these resistive strips as shown in FIG. 9;

[0034]FIG. 11 shows an embodiment equivalent to that shown in FIG. 10but illustrates with increased clarity the advantages of the embodimentshown in FIG. 10;

[0035]FIG. 12 is a schematic illustration of an integrated circuit chipon which an individual one of the embodiments shown in FIGS. 5, 6, 9, 10and 11 may be deposited;

[0036]FIG. 13 is a circuit diagram of a system constituting oneembodiment of this invention;

[0037]FIG. 14 is a schematic representation of the system shown in FIG.13 to provide an enhanced understanding of the operation of the systemshown in FIG. 13;

[0038]FIG. 15 is a simplified schematic representation of the systemshown in FIG. 11 when a single stacked loop is provided;

[0039]FIG. 16 is a simplified schematic representation of the systemshown in FIG. 13 when a pair of stacked loops are provided;

[0040]FIG. 17 is a flattened version of the simplified schematicrepresentation shown in FIG. 16;

[0041]FIG. 18 is a simplified schematic-representation of similar tothat shown in FIG. 16 but with three (3) stacked loops instead of two(2);

[0042]FIG. 19 shows waveforms of an output voltage on an averagingresistor as a function of an input voltage to the averaging resistor;

[0043]FIG. 20 shows a distribution of the output voltage on a strip ofaveraging resistors for two (2) different voltages introduced to theaveraging resistors; and

[0044]FIG. 21 is a block diagram illustrating how two (2) amplifierarrangements each corresponding to that shown in FIG. 18 can beconnected in a cascade arrangement to provide enhanced resolutions indetermining the value of an input voltage.

DETAILED DESCRIPTION OF THE INVENTION

[0045]FIG. 1 illustrates on a schematic basis an analog-to-digital (A-D)converter, generally indicated at 10, of the prior art. The A-Dconverter is of the type known as a flash converter. It includes aplurality of cells generally indicated at 12 a, 12 b, 12 c and 12 d.Although only four (4) cells are shown, it will be appreciated that thefour (4) cells are representative of a number of cells which may beconsiderably greater than four (4). For example, 1024 cells may beemployed to provide a conversion of an analog input voltage to ten (10)binary bits.

[0046] Each of the cells 12 a, 12 b, 12 c and 12 d includes anindividual one of a plurality of pre-amplifiers 14 a, 14 b, 14 c and 14d. Preferably each of these pre-amplifiers is differential so that ithas two (2) inputs and two (2) outputs. One of the inputs to each of thepre-amplifiers 14 a, 14 b, 14 c and 14 d receives an analog input signalon a line 16. The other of the inputs to the pre-amplifiers 14 a, 14 b,14 c and 14 d receives an individual one of progressive fractions of areference voltage. The progressive fractions of the reference voltageare provided by progressive resistors 18 a, 18 b, 18 c and 18 dconnected in a ladder network between a terminal 20 providing areference voltage (e.g. 2 volts) and a terminal 22 providing a lowpotential such as ground.

[0047] Each of the pre-amplifiers 14 a, 14 b, 14 c and 14 d has two (2)outputs depending upon the relative values of the two (2) voltagesintroduced to the pre-amplifier. The two outputs from each of thepre-amplifiers 14 a, 14 b, 14 c and 14 d are respectively introduced toinput terminals of comparators 24 a, 24 b, 24 c and 24 d. Output signalsare respectively provided on output lines 26 a, 26 b, 26 c and 26 d fromthe comparators 24 a, 24 b, 24 c and 24 d. The comparators 24 a, 24 b,24 c and 24 d are respectively included in the cells 12 a, 12 b, 12 cand 12 d.

[0048] Each of the pre-amplifiers 14 a, 14 b, 14 c and 14 d provides apair of relative outputs dependent upon the magnitude of the inputvoltage on the line 16 relative to the magnitude of the particularfraction of the reference voltage introduced to such pre-amplifier. Forexample, the pre-amplifier 14 b produces a higher voltage on the leftoutput line than on the right output line when the input voltage on theline 16 exceeds the particular fraction of the reference voltageintroduced to the pre-amplifier. Similarly, the pre-amplifier 14 bproduces a lower voltage on the left output line than on the rightoutput line when the input voltage on the line 16 is less than theparticular fraction of the reference voltage introduced to thepre-amplifier.

[0049] The differential outputs from each of the pre-amplifiers 14 a, 14b, 14 c and 14 d respectively cause output voltages to be produced bythe comparators 24 a, 24 b, 24 c and 24 d. The output voltage from eachof the comparators 24 a, 24 b, 24 c and 24 d may be-a binary “1” or abinary “0”. For example, the output from the comparator 24 b may be abinary “1” when the magnitude of the input voltage introduced to thepre-amplifier 14 b exceeds the magnitude of the particular fraction ofthe reference voltage introduced to such pre-amplifier. Similarly, theoutput from the comparator 24 b may be a binary “0” when the magnitudeof the input voltage introduced to the pre-amplifier 14 b is less thanthe magnitude of the particular fraction of the reference voltageintroduced to such pre-amplifier.

[0050] It is well known in the art that the binary values of the outputsfrom successive pairs of the comparator 24 a, 24 b, 24 c and 24 d arecompared in exclusive-“or” circuits to determine the digital equivalentof the analog input on the line 16. The particular exclusive-“or”circuit receiving a binary “1” on one input and a binary “0” on theother input provides an indication of the binary signals representativeof the analog input on the line 16. Each exclusive “or” circuit isprogrammed to provide binary indications of the magnitude of the inputvoltage to which such exclusive “or” circuit responds.

[0051] Mismatches may occur for a number of reasons between successivepairs of the cells 12 a, 12 b, 12 c and 12 d. For example, suchmismatches may occur because of deviations at different positions on thesubstrate in the characteristics of the substrate on which the cells areformed. Such mismatches may also occur as a result of deviations in thecharacteristics of a deposition at different positions on thesubstrates. Such cell mismatches may cause inaccurate digitalindications representative of the analog input to be produced. Theseinaccurate indications may particularly result from the fact that 1023comparisons have to be provided to obtain binary indications with anaccuracy of ten (10) binary bits. When the reference voltage has a valuesuch as approximately two volts (2 V.), each progressive fraction of thereference voltage has a value of less than two millivolts (2 mV.). Aswill be appreciated, a cell mismatch does not have to be very large toproduce an error in the binary indications representative of the analoginput on the line 16, particularly when the difference between thevoltages in successive cells is less than two millivolts (2 mv).

[0052]FIG. 2 provides an improved flash converter of the prior art tominimize errors resulting from cell mismatches. This improved flashconverter may be considered to correspond to FIG. 2 of the '550-patent.The embodiment shown in FIG. 2 includes components corresponding tocomponents shown in FIG. 1. These components have the same numericaldesignations as the corresponding components shown in FIG. 1. Theembodiment shown in FIG. 2 also includes a first set of averagingimpedances 30 a, 30 b, 30 c and 30 d and a second set of averagingimpedances 32 a, 32 b, 32 c and 32 d.

[0053] Preferably the impedances 30 a, 30 b, 30 c and 30 d and theimpedances 32 a, 32 b, 32 c and 32 d are resistors. The impedances 30a-30 d and the impedances 32 a-32 d preferably have substantially equalvalues. However, the impedances 30 a-30 d and 32 a-32 d may have anydesired pattern of values other than the equal values specified above.The impedances 30 a-30 d are respectively connected to corresponding(e.g. the left) output terminals in successive pairs of the differentialpre-amplifiers 24 a-24 d. Similarly, the impedances 32 a-32 d arerespectively connected to corresponding (e.g. the right) outputterminals in the successive pairs of the pre-amplifiers 24 a-24 d.

[0054]FIG. 3 illustrates an offset 34 from a desired voltage when a cellmismatch occurs in the prior art embodiment shown in FIG. 1. As will beseen, this offset occurs illustratively at cell 13 in a string of 25cells. All of the other cells (1-12 and 14-25) do not have any offset inthis example. FIG. 3 also illustrates the offset produced at the cell 13when the averaging impedances 30 a-30 d and 32 a-32d are included asshown in FIG. 2.

[0055] As will be seen in FIG. 3, an offset 36 is produced at the cell13 when a cell mismatch occurs at the cell 13 in the embodiment shown inFIG. 2. Offsets of progressively decreasing values are produced for eachof the cells from cell 12 to cell 1 and from cell 14 to cell 25 in theembodiment shown in FIG. 2. This may be seen from the shape of anenvelope 38 in FIG. 3. The envelope 38 in FIG. 3 is advantageous becauseit considerably reduces the offset at cell 13 and because itconsiderably reduces the differential non-linearity between successivepairs of the cells. This may be seen in the gradual decrease of thevalues of the offsets between successive pairs of the cells 13-1 and thecells 13-25.

[0056] The impedances 30 a-30 d and 32 a-32 d provide reductions in theoffset voltage as shown in FIG. 3 by passing a current from the cellproducing the offset voltage to the outputs of successive ones of theadjacent cells in the set. For example, an offset voltage at the cell 12b in FIG. 2 will cause a current to pass from this cell and through theimpedances 30 a and 32 a to the outputs of the pre-amplifier 14 a in thecell 12 a and through the impedances 30 b and 32 b and the impedances 30c and 32 c to the outputs of the respective ones of the pre-amplifiers14 c and 14 d in the cells 12 c and 12 d. The offset voltageprogressively decreases for the cells progressively displaced from thecell (e.g. cell 13 in FIG. 3) producing the offset because the offsetcurrent progressively decreases in relation to the displacement of thecells from the cell producing the offset. Furthermore, the reductionprovided in the offset (e.g. from the offset 34 to the offset 36 in FIG.3) is dependent upon the values of the impedances 30 a-30 d and 32 a-32d. The reduction provided in the offset is increased with decreases inthe values of the impedances 30 a-30 d and 32 a-32 d because theaveraging currents through the impedances are increased with decreasesin the values of these impedances.

[0057]FIG. 4 shows an embodiment of the prior art corresponding to thatshown in FIG. 2 of the '550 patent. The embodiment shown in FIG. 4 showsthe construction of the cells 12 a, 12 b, 12 c and 12 d, andparticularly the construction of the pre-amplifiers 14 a-14 d, inadditional detail since it includes transistors. The construction ofeach of the cells 12 a-12 d is substantially identical. Because of this,only the construction of the pre-amplifier 14 a in the cell 12 a will bedescribed in detail.

[0058] The pre-amplifier 14 a in the cell 12 a includes a pair oftransistors 40 and 42, preferably CMOS and preferably n-type, havingtheir sources connected to one terminal of a source 44 of asubstantially constant current. The second terminal of the source 44 isat a reference potential such as ground. The gates of the transistors 40and 42 respectively receive the voltage on the input line 16 and thevoltage at the left terminal of the reference resistor 18 a in FIG. 2.The drains of the transistors 40 and 42 respectively are common withfirst terminals of resistors 46 and 48. The second terminals of theresistors 46 and 48 receive a positive voltage on a line 50. Connectionsare also made from the drains of the transistors 40 and 42 to theterminals of the averaging impedances 30 a and 32 a also shown in FIG.2.

[0059] Since the current through the source 44 is substantiallyconstant, this current is divided between the transistors 40 and 42dependent upon the relative magnitudes of the voltages on the gates ofthe transistors. Fractions of the currents through the transistors 40and 42 respectively flow through the resistors 46 and 48. The otherfractions of the currents through the transistors 40 and 42 respectivelyflow through the averaging impedances (e.g. resistors) 30 a and 32 a.Thus, not all of the currents flowing through the transistors 40 and 42flow respectively through the averaging impedances 30 a and 30 b since asubstantial portion of such currents respectively flow through theresistors 46 and 48. Since the averaging impedances 30 a and 30 breceive only a portion of the currents flowing through the transistors40 and 42, they have only a limited effectiveness in reducing theeffects of cell mismatches. This is one of the major disadvantages inthe system disclosed and claimed in the '550 patent.

[0060]FIG. 5 illustrates one embodiment of the invention. In thisembodiment, components common to FIGS. 4 and 5 have the same numericaldesignation. These include the transistors 40 and 42 and the source 44of substantially constant current. However, the embodiment shown in FIG.5 includes a pair of current sources 54 and 56 each having an impedanceapproaching infinity. These current sources are respectively connectedbetween a voltage source 58 and the drains of the transistors 40 and 42.The embodiment shown in FIG. 5 also includes a pair of averagingimpedances (e.g. resistors) 60 a and 62 a respectively connected to thedrains of the transistors 40 and 42. The averaging impedances 60 a and60 b are given identifications different from the identifications of thecorresponding impedances in FIG. 4 because they may have lower valuesthan the corresponding impedances in FIG. 4. It will be appreciated thatthe other cells in FIG. 5 may have a construction corresponding to thatspecified above for the cell described in this paragraph.

[0061] Because of the impedance values approaching infinity in theimpedances 54 and 56, little, if any, signal current flows through theseimpedances. Therefore, all of the current flowing in the transistor 40flows through the averaging impedance 60 a and all of the currentflowing in the transistor 42 flows through the averaging impedance 62 a.The increased currents through the averaging impedances 60 a and 62 ballow these averaging impedances to have reduced values relative to thevalues of the averaging impedances 30 a and 32 a in the prior artembodiment shown in FIG. 4. The increased currents through the averagingimpedances 60 a and 62 a provide for an increased reduction by theembodiment of FIG. 5 in the effects of cell mismatches on the output atthe drains of the transistors 40 and 42.

[0062] Transistors 64, 66, 68 and 70 in FIG. 6 are included in anembodiment of the current sources 54 and 56 providing impedancesapproaching infinity. The embodiment shown in FIG. 6 includes a firstpair of transistors 64 and 66 and a second pair of transistors 68 and70. The transistors 64, 66, 68 and 70 are preferably CMOS transistors ofthe p-type. The sources of the transistors 64, 66, 68 and 70 arerespectively common with the voltage source 58. The gates of thetransistors 64 and 66 have a common connection with the drains of thetransistors 64 and 68 and with the drain of a transistor 72. The gate ofthe transistor 72 may receive a positive input voltage. The transistor72 may be a CMOS transistor of the n-type.

[0063] The source of the transistor 72 may have common connections withthe drain of a transistor 74 and with the source of a transistor 76. Thetransistors 74 and 76 may be CMOS transistors of the n-type. The gate ofthe transistor 76 may receive a negative voltage relative to the voltageon the gate of the transistor 72. The drain of the transistor 76 iscommon with the drains of the transistors 66 and 70 and with the gatesof the transistors 68 and 70.

[0064] The positive voltage on the gate of the transistor 72 causes thetransistor to conduct current and to produce a relatively low voltage onthe gates of the transistors 64 and 66. This causes the transistor 66 toconduct current and to produce a high voltage on the drain of thetransistor. In like manner, the low voltage on the gate of thetransistor 76 inhibits the flow of current through the transistor sothat a high voltage is produced on the gates of the transistors 68 and70. This high voltage tends to limit the current through the transistor68 and to produce a low voltage on the drain of the transistor.

[0065] The high voltage on the gate of the transistor 68 also tends tolimit the current through the transistor 68 and to produce a low voltageon the drains of the transistors 64 and 72. This low voltage is oppositeto the high voltage produced on the drain of the transistor 64 by theflow of current through the transistor as described in the previousparagraph. If the characteristics of the transistors in the amplifiershown in FIG. 6 are chosen properly, the effects on the gate of thetransistor 64 by the operation of the transistors 64 and 68 will tend tocancel each other so that little, if any, signal current will flowthrough the transistor 64. This will cause the impedance in thetransistor 64 to approach infinity. In like manner, the transistors 66and 70 will operate in conjunction so that little, if any, current willflow through the transistor 70. This will cause the impedance in thetransistor 70 to approach infinity.

[0066]FIG. 7a shows an envelope 80 (in solid lines) of integralnon-linearity for the prior art embodiment shown in FIG. 1 and alsoshows an envelope 82 (in broken lines) of integral non-linearity for theembodiment shown in FIGS. 5 and 6. In FIG. 7a, the input voltage isshown on the horizontal axis and the integral non-linearity is shown onthe vertical axis where the units are identical to the value of theleast significant bit. The envelopes are shown for averaging oversixteen (16) cells or stages. As will be seen from the envelope 82, theintegral non-linearity may vary from stage to stage by as much asapproximately one half of the value of the least significant bit.However, when the embodiment of the invention shown in FIGS. 5 and 6 isused, the variations in the integral non-linearity in the successivecells or stages, as seen by the envelope 82, are relatively minor. Aswill be seen from FIG. 7a and from the subsequent discussion, the gainin the curve 82 relative to the curve 80 is approximately 3.9. Thiscorresponds to approximately 1.96 bits.

[0067]FIG. 7b shows an envelope 84 (in solid lines) of differentialnon-linearity for the prior art embodiment shown in FIG. 2 and alsoshows an envelope 86 of differential non-linearity for the embodimentshown in FIGS. 5 and 6. In FIG. 7b, the input voltage is shown on thehorizontal axis and the differential non-linearity is shown on thevertical axis for the value of the least significant bit. The envelopes84 and 86 are shown for averaging over sixteen (16) cells or stages.

[0068] As will be seen from the envelope 84, the differential linearityfor the prior art (FIG. 2) may vary from stage to stage by valuesapproaching the value of the least significant bit. However, when theembodiment of the invention shown in FIGS. 5 and 6 is used, thevariations in the differential non-linearity in the successive stages,as seen from the envelope 86 (in broken lines), is relatively minor. Aswill be seen from FIG. 7b and from the subsequent discussion, the gainin the curve 86 relative to the curve 84 is approximately 17.3. Thiscorresponds to approximately 4.1 bits.

[0069] The improvements in integral non-linearity and differentialnon-linearity due to averaging can be understood by considering thediagram of FIG. 8, where the ladder and averaging resistors are shown asone continuous strip of resistive material. The linear input range ofeach amplifier stage is shown at the top of the diagram. When the inputsignal is centered around amplifier m, the current in the averagingresistor contains linear contributions from adjacent amplifiers as well.Beyond the linear range of the amplifiers, the current is clipped. Inthis example, the linear input range overlaps 5 amplifiers. Thereforethe estimated root mean square (rms) offset voltage at stage m isreduced according to

ν_(σm)=ν_(σ)  (1)

[0070] In general the offset after averaging is reduced by νN, where Nis the number of amplifier stages operating in the linear input range atany one instant.

[0071] The improvement in differential non-linearity is even largerbecause it is obtained by taking the difference of two output voltageswhich, after averaging, are highly correlated. Consider the stages n andn+1 in FIG. 8. Without averaging

ν_(δ)=ν_(n)−ν_(n+1)  (2)

[0072] After averaging, $\begin{matrix}{v_{\delta} = {{\frac{v_{n - 2} + v_{n - 1} + v_{n} + v_{n + 1} + v_{n + 2}}{5} - \frac{v_{n - 1} + v_{n} + v_{n + 1} + v_{n + 2} + v_{n + 3}}{5}} = \frac{v_{n - 2}v_{n + 3}}{5}}} & (3)\end{matrix}$

[0073] and the rms value of the difference in offset voltage is given by$v_{\delta\sigma} = \frac{v_{\sigma}}{5}$

[0074] Therefore, differential non-linearity is reduced by the factor N.Returning to the simulation of FIG. 7, where N=16, the improvement of3.9 (1.96-bits) in integral non-linearity and 17.3 (4.1-bits) indifferential non-linearity is consistent with this analysis. The gain of3 (1.5-bits, 9.5-dB) in differential non-linearity reported in the priorart (Technique for Reducing Differential Non-Linearity Errors in FlashA-D Converters, by Kevin Kattman and Jeff Barrow at pages 170-175 of the1991 Digest of Technical Papers in the International Solid StateCircuits Conference) implies an averaging over N=3 stages. This analysiswould predict a corresponding gain of 1.73 (0.8-bits, 4.7-dB) inintegral non-linearity, which would reduce maximum harmonics by asimilar factor. This was indeed found to be the case.

[0075] For the actual design, applicant used folding and interpolation,which complicates the above first-order analysis, but the principle, andobtainable integral non-linearity and differential non-linearity gainsremain the same. This distributed approach has the effect of making theinput transistors look bigger. To achieve the same differentialnon-linearity performance without averaging, the input transistors wouldhave to increase in area by N², or 256 times for N=16. Such enormousgains in differential non-linearity and integral non-linearity fromaveraging allows the use of almost minimum size devices in the gainstages.

[0076]FIG. 9 shows an arrangement corresponding to that shown in FIG. 5.This embodiment shows eight (8) cells respectively designated as “1”through “8”. Each of the cells 1-8 is considered to be constructed in amanner corresponding to that shown in FIG. 5. However, in the embodimentshown in FIG. 9, the resistors 18 a, 18 b, 18 c and 18 d are replaced bya strip 92 of resistive material deposited on an integrated circuit chip90 (FIG. 12) holding the circuitry shown in FIG. 5. As will be seen, theresistive strip 92 is disposed in a direction transverse to the cells,which are designated as 1-8 in FIG. 9. The resistive strip 92 is tappedat progressive positions to form the resistors 18 a, 18 b, 18 c and 18d.

[0077] In like manner, the resistors corresponding to the resistor 60 ain FIG. 5 are formed by a strip 94 of resistive material deposited onthe integrated circuit chip 90. The resistive strip 94 is disposed in adirection substantially parallel to, but displaced from, the resistivestrip 92. The resistive strip 94 is tapped at progressive positions toform such resistors. The resistors corresponding to the resistor 62 a inFIG. 5 are also formed by a strip 96 of resistive material deposited onthe integrated circuit 90. The resistive strip 96 is substantiallyparallel to, but displaced from, the resistive strips 92 and 94. Theresistive strip 96 is tapped at progressive positions to form suchresistors.

[0078] In the embodiments shown in FIGS. 5 and 9 and in the prior artembodiments shown in FIGS. 2 and 4, the averaging resistors haveopen-ended terminations at their opposite ends. For example, theresistive strips 94 and 96 have open-ended terminations. Because ofthis, in the extreme left cell or in the extreme right cell in FIG. 9,the averaging resistors will pull in one direction only, causing theseoffsets and non-linearity. It will also be appreciated that the effectsof this in the cells immediately adjacent to the extreme left andextreme right cells also cannot be completely compensated.

[0079]FIG. 10 shows an embodiment in which effective compensations areprovided even at the positions of the open end terminations of theaveraging resistors. This is accomplished by connecting the right openend of each of the sets of averaging impedances to the left open end ofthe other set of averaging resistors. For example, the open-endedterminal in the averaging impedance 60 a (FIG. 5) in one set isconnected to the open-ended terminal in the averaging resistor at theright end of the set including the averaging impedance 62 a. In likemanner, the open-ended terminal in the averaging impedance 62 a (FIG. 5)in the second set is connected to the open ended terminal at the rightend of the set including the averaging impedance 60 a.

[0080]FIG. 11 shows a re-arrangement of the different elements in theembodiment shown in FIG. 10 to show the symmetry of the arrangement ofFIG. 10. As will be seen, the straight line arrangement in FIG. 10 isre-arranged into a circle in the embodiment shown in FIG. 11. Thedifferent strips of resistors in FIG. 11 are respectively designated as92 a, 94 a and 96 a to correspond to the resistive strips 92, 94 and 96in FIG. 9. In the embodiment shown in FIG. 11, one open-end of each ofthe strips 94 a and 96 b are connected to the other open end of theother strip. This results in two (2) cross-overs 98 a and 98 b betweenthe strips 94 a and 96 a. The two (2) crossovers 98 a and 98 b areelectrically insulated from each other so that the resistive strip 94 awill be electrically insulated from the resistive strip 96 a.

[0081] The embodiments of the invention shown in the drawings anddescribed above have certain advantages over the prior art, particularlythe prior art shown in FIGS. 2 and 4. The embodiments of the inventioncompensate for cell mismatches with much greater effect than in theprior art. This may be seen from the considerable decrease in integralnon-linearity and differential non-linearity by the embodiments of thisinvention relative to the systems of the prior art. This results in partfrom the passage of all of the signal current through the averagingimpedances in the embodiments of this invention. The passage of all ofthe signal current through the averaging impedances results from theinclusion in the cells of load impedances having values approachinginfinity.

[0082] The embodiments of this invention are also advantageous inminimizing the effects of cell mismatches in the averaging impedanceshaving open ended terminations in the prior art. In the embodiments ofthis invention, the open ended terminations at each end in each set ofaveraging impedances are connected to the open ended terminations at theopposite end of the other set of averaging impedances. For example, theimpedance 60 a at the left end of the set including the impedance 60 ais connected to the impedance at the right end of the set including theimpedance 62 a.

[0083]FIG. 13 indicates a system which constitutes an improvement of thesystem shown in FIG. 11. The system shown in FIG. 13 includes theresistor strips 94 a and 96 a shown in FIG. 11. It also includes thecross-overs 98 a and 98 b to form the resistor strips 94 a and 96 a intoa single closed-loop strip. The system shown in FIG. 13 also providesthe amplifiers 1 a-8 a. These amplifiers receive the input voltage onthe line 16 and progressive fractions of a reference voltage on theresistance strip 92 a.

[0084] The amplifiers la-8 a are shown as being unshaded because eachamplifier provides a positive output when the input voltage exceeds theparticular fraction of the reference voltage introduced to theamplifier. As will be seen, the resistance strip 92 a is tapped atprogressive positions along its length to introduce progressivefractions of the reference voltage to successive ones of the amplifiers1 a-8 a. Similarly, the resistance strips 94 a and 96 a are tapped atprogressive positions along their lengths to provide outputs forprogressive ones of the amplifiers 1 a-8 a.

[0085] As will be seen in FIG. 13, the resistance strip 92 a is disposedradially inwardly from its position in FIG. 11. This is to allow theresistance strip 92 a to be looped a second time around the support(e.g. the integrated circuit chip) on which it is disposed. This secondloop of the resistance strip is designated in FIG. 13 as 92 b. Taps atprogressive positions along the second loop 92 b of the resistance stripare connected to input terminals of amplifiers respectively designatedas 9 a-16 a. The output terminals of the amplifiers 9 a-16 arespectively have common connections with the output terminals of theamplifiers la-8 a.

[0086] The amplifiers 9 a-16 a are shown as shaded. One reason is thatthe amplifiers 9 a-16 a may be considered as folded relative to theamplifiers la-8 a. In other words, the amplifiers 1 a-8 a may beconsidered as providing progressive outputs in the positive directionand the amplifiers 9 a-16 a may be considered as providing progressiveoutputs in the negative direction. Thus, the outputs of the amplifiersla-8 a may be considered to provide the rising side of an equilateraltriangle and the outputs of the amplifiers 9 a-16 a may be considered toprovide the falling side of the equilateral triangle.

[0087] When one of the amplifiers la-8 a provides an output indicatingthe rising side of the equilateral triangle, it provides a positiveoutput when the input voltage on the line 16 exceeds the particularfraction of the reference voltage introduced to such amplifier. However,when one of the amplifiers 9 a-16 a provides an output indicating thefalling side of the equilateral triangle, it provides a negative outputwhen the input voltage on the line 16 exceeds the particular fraction ofthe reference voltage introduced to such amplifier.

[0088] For each of the amplifiers 1 a-8 a, a positive output is producedwhen the input voltage is greater than the particular fraction of thereference voltage introduced to such amplifier. For each of theamplifiers 9 a-16 a, a negative output is produced when the inputvoltage is greater than the particular fraction of the reference voltageintroduced to such amplifier. This production of an output voltage of anopposite polarity from the amplifiers 9 a-16 a relative to the outputvoltage from the amplifiers 1 a-8 a results from the folded relationshipdiscussed above between the amplifiers 1 a-8a and 9 a-16 a.

[0089] The relationship discussed above and shown in FIG. 13 has certainimportant advantages. It provides for minimal lengths in the resistivestrips 94 a and 96 a since the resistive strips 94 a and 96 service morethan one amplifier. It also provides the disposition of the resistivestrip 92 a and the extension 92 b in a minimal amount of space. It alsoprovides a considerable number of outputs with a minimal number ofoutput terminals. For example, the outputs of sixteen (16) amplifiersare provided by eight (8) pairs of output terminals in FIG. 13. Thisreduces the number of comparators needed to provide the outputs. Thearrangement shown in FIG. 13 accordingly provides a compact andefficient system for determining the value of the input voltage on theline 16.

[0090] The arrangement shown in FIG. 13 implements a two (2)-timesfolding. It will be appreciated that the number of folds can beincreased to any desired value in the system of this invention. This maybe seen from FIG. 14 which resembles a drill bit in the sense thatalternate layers have a spiral pattern downwardly along the drill bit.In FIG. 13, successive amplifier layers are connected with alternatepolarities. These successive layers are differentiated from one anotherby light shadings for alternate ones 102 a, 102 c, (designated as“positive layer”) of the layers and by dark shadings for the other ones(e.g. 102 b, 102 d designated as “negative layer”) for the other ones ofthe layers.

[0091]FIG. 14 also shows a polystrip 104 (schematically providing theaveraging resistors represented as in a closed loop) and also showsprojections from corresponding positions in the different layers 102a-102 d to positions on the poly strip 104. It will be appreciated thatthe showing in FIG. 14 is only schematic since it is a three(3)-dimensional representation and since three (3)-dimensionalrepresentations cannot be easily provided on an integrated circuit chipsuch as the chip 90 shown in FIG. 12.

[0092]FIG. 15 illustrates on a simplified basis an actual layout in theintegrated circuit 90 for the amplifiers 1-8 in FIG. 11. It will beappreciated that a similar layout may be provided on the integratedcircuit chip 90 for the amplifiers 1 a-8 a and 9 a-16 a as shown in FIG.13. As shown in FIG. 15, the-taps for the averaging resistors connectedto the amplifiers 1 a-4 a are shown along one horizontal line on thechip 90 and the taps for the averaging resistors connected to theamplifiers 5 a-8 a are shown along another horizontal line on the chip.As shown in FIG. 15, the taps for the amplifiers 5 a-8 a are staggeredin position relative to the taps for the amplifiers la-4 a. The layoutof the taps for the amplifiers 1 a-8 a may accordingly be represented ona two (2)-dimensional basis as indicated by a chart 106 in FIG. 15.

[0093]FIG. 16 illustrates a flattened version of the system shown inFIG. 13. As shown in FIG. 16, the taps for the averaging resistors forthe amplifiers 1 a-8 a are shown below the taps for the averagingresistors for the amplifiers 9 a-16 a. This is for convenience inrepresentation since the taps for the averaging resistances in theamplifiers 1 a-8 a respectively correspond to the taps for the averagingresistors for the amplifiers 9 a-16 a. Similarly, the taps for theaveraging resistors for the amplifiers 1 a-8 a are shown in FIG. 17 forpurposes of convenience and clarification as horizontally displaced fromthe taps for the averaging resistors for the amplifiers 9 a-16 a.

[0094] It has been previously indicated that more than two (2) loops(e.g. amplifiers 1 a-8 a and 9 a-16 a) may be folded. FIG. 18 shows anarrangement in which three (3) loops may be folded. In FIG. 18, thefirst group (1 a-8 a) and third group (17 a-24 a) of amplifiers areshown as unshaded. These provide progressive positive values for thesuccessive amplifiers in the loop. The second group (9 a-16 a) ofamplifiers are shown as shaded. These provide progressively negativevalues for the successive amplifiers in the loop.

[0095] The outputs of the amplifiers 1 a-24 a in FIG. 18 may becascaded. For example, three (3) additional loops corresponding to thoseshown in FIG. 18 may be provided. The outputs of the amplifiers 1-24 ain the first three (3) loops may then be introduced as the inputs to thecorresponding amplifiers in the cascade arrangement formed by the three(3) additional loops. The construction of the three (3) additional loopscorresponds to the construction of the first three (3) loops.

[0096]FIG. 19 indicates a function of the input voltages at progressivevertical positions. The first group of amplifiers 1 a-8 a is indicatedfor the portion of the function curves between a line 112 and a line129. The second group of amplifiers 9 a-16 a is indicated for theportion of the function curves between the line 129 and a line 130. Thethird group of amplifiers 17 a-24 a is indicated for the portion of thefunction curves to the right of the line 130.

[0097]FIG. 19 indicates the output voltage from each of the amplifiers 1a-24 a. This is indicated for progressive values of the input voltageinitially for the amplifiers 1 a-8 a in the first group, then for theamplifiers 9 a-16 a in the second group and then for the amplifiers 17a-24 a in the third group. As will be seen illustratively for theamplifiers la-8a in the first group, the differential voltage producedfor each of such amplifiers has a zero (0) output for each of theprogressive amplifiers 1 a-8 a at progressive increases in the inputvoltage.

[0098] The eight (8) outputs from the embodiment shown in FIG. 19 may befolded again in a cascade relationship to produce four (4) outputs. Thefolding may be in an arrangement similar to that shown in FIG. 18. Inthis arrangement, the first four of the eight (8) outputs may be foldedin a positive direction for increases of the progressive fractions ofthe reference voltage and the last four (4) of the outputs may be foldedin a negative direction for increases of the progressive fractions ofthe reference voltage. The outputs from the amplifiers in FIG. 1 areshown on a block diagram in FIG. 21 at 110 and the folding in thecascade arrangement is shown on a block diagram basis at 112 in FIG. 21.

[0099]FIG. 19 indicates at 112 a vertical line in which the inputvoltage is determined by the amplifiers shown in FIG. 19 to have a valueof V1. The upper schematic representation in FIG. 20 constitutes avoltage distribution curve which indicates the voltage distribution onthe resistor strip 94 a when the input voltage Vin=V1.

[0100] The voltage distribution at progressive taps on the resistorstrips 94 a is illustrated by broken lines at 116 in FIG. 20. Thevoltage distribution is also indicated by a shaded ellipse 118 in FIG.20. As shown in FIG. 20, there are 16 taps on the resistor strip 94 a.This corresponds to a folding of eight (8) amplifiers in the positivedirection and then a folding of eight (8) additional amplifiers in anegative direction. These taps are indicated by intersections ofvertical lines with the resistor strip 94 a. One of these intersectionsis illustrated at 120 in FIG. 20.

[0101] The zero crossings of the voltage at progressive positions on theresistor strip 94 a are indicated at 122 and 124 in FIG. 20 whenV_(in)=V1. One of these zero crossings is for the positive foldingprovided by the amplifiers la-8 a. The other zero crossing is for thenegative folding provided by the amplifiers 9 a-16 a. The vertical linesindicate the current outputs from the transistors such as the transistor94 in FIG. 5. One of these vertical lines is indicated at 126 in FIG. 20when V_(in)=V1.

[0102]FIG. 19 also includes a second voltage distribution curve 128.This distribution curve includes a vertical line 130 in which the inputvoltage V_(in) is determined by the amplifiers shown in FIG. 18 to havea value of V2. The lower drawing in FIG. 20 indicates the distributionof voltage on the resistor strip 94 a when V_(in)=V2. This voltagedistribution is indicated by a shaded ellipse 132. This ellipse has adifferent shape than the ellipse 118. It also has zero crossings at 13Aand 136. These zero crossings are at different positions on the resistorstrip 94 a than the zero crossings 122 and 124 in the upper distributioncurve in FIG. 20.

[0103] Although this invention has been disclosed and illustrated withreference to particular embodiments, the principles involved aresusceptible for use in numerous other embodiments which will be apparentto persons of ordinary skill in the art. The invention is, therefore, tobe limited only as indicated by the scope of the appended claims.

1. In combination in a monolithic integrated circuit chip, a pluralityof repetitive cells each having a first branch responsive to a digitalinput voltage and having a second branch responsive to an individual oneof progressive fractions of a reference voltage to provide an outputsignal representative of any difference between the input voltage andthe individual one of the progressive fractions of the referencevoltage, an impedance network comprising a first set of impedanceelements each connected to the first branches of first individual pairsof successive ones of the repetitive cells and a second set of impedanceelements each connected to the second branches of second individualpairs of the successive ones of the repetitive cells, the first set ofthe impedance elements defining a first impedance strip on the chip andthe second set of the impedance elements defining a second impedancestrip on the chip, and each of the impedance elements in the first setbeing connected to repetitive cells which are responsive to progressivefractions of the reference voltage, such progressive fractionsrepresenting voltage differences between the successive cells connectedto such impedance elements greater than the voltage difference betweensuccessive ones of the progressive fractions of the reference voltage,each of the impedance elements in the second set being connected torepetitive cells which are responsive to the progressive fractions ofthe reference voltage, such progressive fractions representing voltagedifferences between the successive cells connected to such impedanceelement greater than the voltage difference between successive ones ofthe progressive fractions of the reference voltage.
 2. In a combinationas set forth in claim 1, means for reading the outputs from thesuccessive cells in sequence in accordance with the progressivefractions of the reference voltage connected to such cells.
 3. In acombination as set forth in claim 1, the repetitive cells in theplurality being divided into groups, the cells in each group beingresponsive to progressive fractions of the reference voltage throughindividual ranges of values, the cells in each group being in a foldedrelationship to the cells in the other groups.
 4. In a combination asset forth in claim 3, means for applying the outputs from the cells in asecond folded relationship corresponding to the folded relationship forthe repetitive cells in the plurality.
 5. In a combination as set forthin claim 1, the second impedance strip being continuous with the firstimpedance strip.
 6. In a combination as set forth in claim 1, means forreading the outputs from the successive cells in sequence in accordancewith the progressive fractions of the reference voltage connected tosuch cells, the repetitive cells in the plurality being divided intogroups, the cells in each group being responsive to progressivefractions of the reference voltage through individual ranges of values,the cells in each group being in a folded relationship to the cells inthe other groups, means for applying the outputs from the cells in asecond folded relationship corresponding to the folded relationship forthe repetitive cells in the plurality, the second impedance strip beingcontinuous with the first impedance strip.
 7. In a combination as setforth in claim 1, means for sequentially determining the outputs of thecells which are responsive to successive ones of the progressivefractions of the reference voltage.
 8. In a combination as set forth inclaim 1, means for alternating the polarity of the output of thesuccessive ones of the cells connected to each individual one of theimpedance elements in the first and second sets.
 9. In a combination asset forth in claim 6, means for sequentially determining the outputs ofthe cells which are responsive to successive ones of the progressivefractions of the reference voltage, means for alternating the polarityof the output of the successive ones of the cells connected to eachindividual one of the impedance elements in the first and second sets.10. In a monolithic chip, a first plurality of averaging impedancesdisposed at progressive positions in a first printed circuit strip, asecond plurality of averaging impedances disposed at progressivepositions in a second printed circuit strip, the first and secondprinted circuit strips being connected to each other to define a closedloop, and first and second pluralities of cells, each successive pair ofthe cells in the first plurality being connected to the opposite ends ofan individual one of the averaging impedances in the first plurality andto the opposite ends of an individual one of the averaging impedances inthe second plurality, each successive pair of the cells in the secondplurality being connected to the opposite ends of an individual one ofthe averaging impedances in the first plurality and to the opposite endsof an individual one of the averaging impedances in the secondplurality, the cells in the second plurality being responsive toprogressive fractions of the reference voltage greater in value than theprogressive fractions of the reference voltage to which the cells in thefirst plurality are responsive.
 11. In a monolithic chip as set forth inclaim 10, each of the cells in the first plurality having a first branchresponsive to a digital input voltage and having a second branchresponsive to an individual one of progressive fractions of a referencevoltage to provide an output signal representative of any differencebetween the input voltage and the individual one of the progressivefractions of the reference voltage.
 12. In a monolithic chip as setforth in claim 10, the impedance elements in the first and second setsin each individual one of the cells being connected to the cellsuccessive to the individual one of the cells to provide current fromsuch individual one of the cells to the successive cells and to reducethe effects of cell mismatches on the output signal.
 13. In a monolithicchip as set in claim 10, a plurality of high impedance current sourceseach connected to an individual one of the cells, the high impedancecurrent sources having a high impedance value in comparison to the valueof the impedance elements in the first and second sets to reduce theeffects of cell mismatches on the output signals.
 14. In a monolithicchip as set forth in claim 13, the impedances in the first and secondpluralities being connected in the cells to receive the currents flowingthrough the cells and to reduce the effects of cell mismatches on theoutput signals and the high impedance current sources being constructedto prevent the passage of load bearing current through the highimpedance currents sources.
 15. In a monolithic chip as set forth inclaim 11, the impedance elements in the first and second sets in eachindividual one of the cells being connected to the cell successive tothe individual one of the cells to provide current from such individualone of the cells to the successive cells and to reduce the effects ofcell mismatches on the output signal, a plurality of high impedancecurrent sources each connected to an individual one of the cells, thehigh impedance current sources having a high impedance value incomparison to the value of the impedance elements in the first andsecond sets to reduce the effects of cell mismatches on the outputsignals, the impedances in the first and second pluralities beingconnected in the cells to receive the currents flowing through the cellsand to reduce the effects of cell mismatches on the output signals andthe high impedance current sources being constructed to prevent thepassage of load bearing current through the high impedance currentssources.
 16. In a combination as set forth in claim 10, means forsequentially determining the outputs of cells which are responsive toprogressive fractions of the reference voltage.
 17. In a combination asset forth in claim 10, the outputs of the cells in the first pluralitybeing connected in a first folded relationship to the outputs of thecells in the second plurality, and means for connecting the outputs ofthe cells in the first and second pluralities in a second foldedrelationship corresponding to the first folded relationship.
 18. In amonolithic chip formed with an integrated circuit including a number ofrepetitive cells for producing output signals in response to respectiveinputs, each of such cells including a pair of circuit branches toprovide for the flow of current through such pair of circuit branchesand to provide for the production of a cell output signal, each of thebranches including terminals for providing connections, the improvementfor reducing the effects of cell mismatches on such output signals,comprising an impedance network comprising a set of impedance elementseach operatively coupled to corresponding terminals in respective pairsof the circuit branches and each connected in a circuit with theconstant current source to constitute a current-carrying load elementaffecting the production of the load output signal from such branches toreduce the effects of load mismatches on the output signals, and aplurality of high impedance current sources each connected in anindividual one of the branches and each having an impedance value higherthan the impedance values of the impedance elements, the repetitivecells being divided into sub-sets, each of the impedance elements beingconnected to individual ones of the repetitive cells in the differentsubsets.
 19. In a monolithic chip as set forth in claim 18, the cellsconnected to the impedance elements in each alternate sub-set providingan output of one polarity and the cells connected to the impedanceelements in the other sub-sets providing an output of an oppositepolarity.
 20. In a monolithic cell as set forth in claim 18, the cellsin each sub-set being interleaved on the integrated circuit chip withthe corresponding ones of the cells in another one of the sub-sets. 21.In a monolithic chip as set forth in claim 18 wherein each of thebranches is load bearing and wherein each of the impedance elementscouples the load bearing of an individual pair of corresponding branchesin successive cells to reduce the effects of load mismatches on theoutput signals.
 22. In a monolithic chip as set forth in claim 18wherein the impedance elements connected to the terminals in eachindividual one of the cells form load-bearing circuits not including thehigh impedance current sources in such individual one of the cells andwherein the load-bearing circuits include constant current sources inthe cell successive to such individual one of the cells.
 23. In amonolithic chip as set forth in claim 18 wherein the impedance elementsin the set have relatively low values in comparison to the impedancevalues of the high impedance current sources.
 24. In a monolithic chipas set forth in claim 18, each of the branches is load bearing andwherein each of the impedance elements couples the load bearing of anindividual pair of corresponding branches in successive cells to reducethe effects of load mismatches on the output signals, the impedanceelements connected to the terminals in each individual one of the cellsform load-bearing circuits not including the high impedance currentsources in such individual one of the cells and wherein the load-bearingcircuits include constant current sources in the cell successive to suchindividual one of the cells, the impedance elements in the set haverelatively low values in comparison to the impedance values of the highimpedance current sources.
 25. In a monolithic chip as set forth inclaim 20, means for sequentially determining the outputs of cells whichare responsive to progressive fractions of the reference voltage, meansfor sequentially determining the outputs of cells which are responsiveto progressive fractions of the reference voltage, in a monolithic chipformed with an integrated circuit including a number of repetitive cellsfor producing output signals in response to respective inputs, each ofsuch cells including a pair of circuit branches to provide for the flowof current through such pair of circuit branches and to provide for theproduction of a cell output signal, each of the branches includingterminals for providing connections, the improvement for reducing theeffects of cell mismatches on such output signals, comprising animpedance network comprising a set of impedance elements eachoperatively coupled to corresponding terminals in respective pairs ofthe circuit branches and each connected in a circuit with the constantcurrent source to constitute a current-carrying load element affectingthe production of the load output signal from such branches to reducethe effects of load mismatches on the output signals, and a plurality ofhigh impedance current sources each connected in an individual one ofthe branches and each having an impedance value higher than theimpedance values of the impedance elements, the repetitive cells beingdivided into sub-sets, each of the impedance elements being connected toindividual ones of the repetitive cells in the different subsets, thecells connected to the impedance elements in each alternate sub-setproviding an output of one polarity and the cells connected to theimpedance elements in the other sub-sets providing an output of anopposite polarity.
 26. In a combination as set forth in claim 18, meansfor sequentially determining the outputs of the progressive cells ineach of the progressive sub-sets where the progressive cells indicateprogressive values of the input voltage and the progressive sub-setsindicate progressive values of the input voltage.
 27. In a combinationas set forth in claim 18, the repetitive cells in each sub-set beingfolded in a first particular relationship to the cells in the othersub-sets, and means for folding the outputs of the cells in thesub-sets.
 28. In combination for converting an analog voltage to adigital voltage, a plurality of differential amplifiers each havingfirst and second input terminals, first means for providing for theintroduction of an input voltage to the first one of the input terminalsin each of the differential amplifiers, second means for providing forthe production of progressive fractions of a reference voltage, thirdmeans for providing for the introduction of an individual one of theprogressive fractions of the reference voltage to each of the secondinput terminals, each of the differential amplifiers being constructedto provide a first output when the input voltage on the first terminalof such differential amplifier exceeds the voltage on the secondterminal of the differential amplifier and to provide a second outputwhen the voltage on the second terminal of the differential amplifierexceeds the voltage on the first terminal of the differential amplifier,first impedance means providing a low impedance value and connectingcorresponding terminals in successive ones of the differentialamplifiers to provide, in such differential amplifiers through suchimpedance means, load-bearing currents affecting the relative values ofthe first and second outputs, thereby to reduce the effects of cellmismatches on said output signals, and fourth means connected in each ofthe differential amplifiers and providing a high impedance value in eachof the differential amplifiers relative to the impedance value of suchfirst impedance means to provide for the flow of the load bearingcurrents through such first impedance means, the differential amplifiersin the plurality being divided into sub-sets, the terminals incorresponding differential amplifiers in the different sub-sets havingcommon connections to the first impedance means.
 29. In a combination asset forth in claim 21 wherein each of the differential amplifiersincludes at least one transistor and wherein the fourth means connectedin each of the differential amplifiers provides an impedance approachinginfinity to restrict the flow of load-bearing current through suchdifferential amplifier.
 30. In a combination as set forth in claim 21wherein each of the differential amplifiers includes first and secondbranches each including one of the fourth means, the first branch ineach of the differential amplifiers being operative to produce a currentthrough the first impedance means in such branch in accordance with therelative values of the input voltage and the individual one of theprogressive fractions of the reference voltage and the second branchbeing operative to produce a current through the first impedance meansin such branch in accordance with the relative values of the inputvoltage and the individual one of the progressive fractions of thereference voltage.
 31. In a combination as set forth in claim 28 whereinthe differential amplifiers in each alternate sub-set are foldedrelative to the differential amplifiers in the other sub-sets.
 32. In acombination as set forth in claim 28 wherein the differential amplifiersin alternate sub-sets have outputs changing in a particular directionfor increases in the progressive fractions of the reference voltagerelative to the direction of the changes in the outputs of thedifferential amplifiers in the other sub-sets.
 33. In a combination asset forth in claim 31, means for cascading the outputs of thedifferential amplifiers by providing an additional folding of suchoutputs.
 34. In a combination as set forth in claim 32, means forcascading the outputs of the differential amplifiers by changing suchoutputs in a particular direction for a first group of successiveoutputs and then in a second direction opposite to the first directionfor a second group of successive outputs immediately following theoutputs in the first group.
 35. In combination for converting an analogvoltage to a digital voltage, a plurality of differential amplifierseach having first and second input terminals, first means for providingfor the introduction of an input voltage to the first one of the inputterminals in each of the differential amplifiers, second means forproviding for the production of progressive fractions of a referencevoltage, third means for providing for the introduction of an individualone of the progressive fractions of the reference voltage to each of thesecond input terminals, each of the differential amplifiers beingconstructed to provide a first output when the input voltage on thefirst terminal of such differential amplifier exceeds the voltage on thesecond terminal of the differential amplifier and to provide a secondoutput when the voltage on the second terminal of the differentialamplifier exceeds the voltage on the first terminal of the differentialamplifier, first impedance means providing a low impedance value andconnecting corresponding terminals in successive ones of thedifferential amplifiers to provide in such differential amplifiersthrough such impedance means load-bearing currents affecting therelative values of the first and second outputs, thereby to reduce theeffects of cell mismatches on said output signals, and fourth meansconnected in each of the differential amplifiers and providing a highimpedance value in each of the differential amplifiers relative to theimpedance value of such first impedance means to provide for the flow ofthe load bearing currents through such first impedance means, thedifferential amplifiers in the plurality being disposed in sub-sets, thedifferential amplifiers in the sub-sets being disposed in an interleavedrelationship, corresponding differential amplifiers in the differentsub-sets having common connections to the first impedance means.
 36. Ina combination as set forth in claim 35 wherein the high impedance meansin each of the differential amplifiers includes at least one transistorand wherein the fourth means in each of the differential amplifiersprovides an impedance approaching infinity to restrict the flow ofload-bearing current through the high impedance means and wherein thedifferential amplifiers in each sub-set provide outputs of an oppositepolarity relative to the polarity of the outputs of the differentialamplifiers in adjacent sub-sets.
 37. In a combination as set forth inclaim 35 wherein the differential amplifiers in alternate sub-sets haveoutputs with a folded relationship relative to the output of thedifferential in the other sub-sets.
 38. In a combination as set forth inclaim 37, the first impedance means including a plurality of impedancesand providing a voltage from each of such impedances, and means forproviding a folded relationship for the voltages from the impedances inthe plurality corresponding to the folded relationship for the outputsfrom the differential amplifiers.
 39. In combination for determining therelative values of an input voltage and individual ones of progressivefractions of a reference voltage, a plurality of current cells eachhaving first and second branches connected in a differentialrelationship to determine the relative values of the input voltageintroduced to the cell and the individual one of the progressivefractions of the reference voltage introduced to the cell, a network ofimpedance elements each connected between a pair of correspondingbranches in successive ones of the cells, a plurality of first meanseach included in an individual one of the branches for providing aload-bearing current in such individual one of the branches, and aplurality of second means each included in an individual one of thebranches for providing for the flow of the load bearing currents throughthe impedance elements in the network, the cells being divided intosub-sets, the cells in alternate sub-sets having an opposite polarity tothe cells in the other sub-sets, there being a corresponding number ofcells in each of the sub-sets, the successive cells in each sub-setresponding to progressively increased fractions of the referencevoltage, corresponding elements in the different sub-sets beingconnected to the same impedance elements.
 40. In a combination as setforth in claim 39, the cells in the successive sub-sets having a foldedrelationship to each other to provide for progressively increasingvalues in the successive cells in alternate sub-sets and forprogressively decreasing values in successive cells in the othersub-sets.
 41. In a combination as set forth in claim 39, the sub-sets ofcells constituting first sub-sets, the cells being first cells, therebeing second cells divided into second sub-sets, the second cells inalternate ones of the second sub-sets having an opposite polarity to thesecond cells in the other ones of the second sub-sets, there being acorresponding number of second cells in each of the second sub-sets, thesecond cells in each of the second sub-sets responding to progressivelyincreased fractions of the reference voltage, corresponding cells in thedifferent ones of the second sub-sets being connected to the sameimpedance elements, the outputs of the first cells in each of the firstsub-sets being connected as inputs to the corresponding ones of thesecond cells in the second sub-sets.
 42. In a combination as set forthin claim 39, means for sequentially determining the outputs of thesuccessive cells in each of the successive sub-sets.
 43. In acombination as set forth in claim 41, means for sequentially determiningthe outputs of successive ones of the first cells in each of the firstsuccessive sub-sets and for thereafter sequentially determining theoutputs of successive ones of the second cells in each of the secondsuccessive sub-sets.
 44. In combination for converting an analog voltageto a digital voltage, a plurality of differential amplifiers each havingfirst and second input terminals, first means for providing for theintroduction of an input voltage to the first one of the input terminalsin each of the differential amplifiers, second means for providing forthe production of progressive fractions of a reference voltage, thirdmeans for providing for the introduction of an individual one of theprogressive fractions of the reference voltage to each of the secondinput terminals, each of the differential amplifiers being constructedto provide a first output when the input voltage on the first terminalof such differential amplifier exceeds the voltage on the secondterminal of the differential amplifier and to provide a second outputwhen the voltage on the second terminal of the differential amplifierexceeds the voltage on the first terminal of the differential amplifier,a plurality of first impedance means each providing a low impedancevalue and connecting corresponding terminals in an individual one of asuccessive pair of the differential amplifiers to provide in suchindividual one of the successive pairs of differential amplifiersthrough such impedance means load bearing currents affecting therelative values of the first and second outputs for such successive pairof the differential amplifiers, thereby to reduce the effects of cellmismatches on said output signals, and fourth means connected in each ofthe differential amplifiers and providing a high impedance value in eachof the differential amplifiers relative to the impedance value of suchfirst impedance means to provide for the flow of the load bearingcurrents through such first impedance means, each of the first impedanceconnecting corresponding terminals in the associated successive pair ofthe differential amplifiers for different ones of the progressivefractions of the reference voltage to provide in such associated pair ofthe differential amplifiers through such impedance means and bearingcurrents affecting the relative values of the first and second outputsfor each of the different ones of the progressive fractions of thereference voltage, thereby to reduce the effects of cell mismatches onthe output signals.
 45. In a combination as set forth in claim 36, thedifferent ones of the progressive fractions of the reference voltageassociated with the first impedance means for each individual one of thesuccessive pairs of the differential amplifiers having a particularrepetitive relationship to one another.
 46. In a combination as setforth in claim 37, the first impedance means in the plurality beingconnected in a closed loop and the successive ones of the impedancemeans in the plurality being responsive to successive ones of theprogressive fractions of the reference voltage in the particularrepetitive relationship.